DocumentCode
3381792
Title
The importance of retardation in PEEC models for electrical interconnect and package (EIP) applications
Author
Ruehli, Albert ; Chiprout, Eli
Author_Institution
Res. Div., IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fYear
1995
fDate
2-4 Oct 1995
Firstpage
232
Lastpage
234
Abstract
Partial Element Equivalent Circuit (PEEC) models have been employed in both the EMI (Electro-Magnetic Interference) as well as the EIP (Electrical Interconnect and Package) areas. It is generally assumed that the retardation between the circuit elements can be ignored for EIP problems since the radiated fields are not of interest for this application. In this paper, we give some insight into the importance of retardation for EIP problems
Keywords
equivalent circuits; integrated circuit interconnections; integrated circuit packaging; EIP; PEEC model; electrical interconnect and package; partial element equivalent circuit; retardation; Circuit stability; Delay; Equivalent circuits; Frequency; Integral equations; Integrated circuit interconnections; Integrated circuit modeling; Integrated circuit packaging; Interference; Scattering;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Performance of Electronic Packaging, 1995
Conference_Location
Portland, OR
Print_ISBN
0-7803-3034-X
Type
conf
DOI
10.1109/EPEP.1995.524902
Filename
524902
Link To Document