A 1.8V 100MS/s 10-bit pipelined folding A/D converter with 9.49 ENOB at Nyquist frequency

The design issues of a 10-bit 100MSample/s analog-to-digital (A/D) converter with pipelined folding architecture are described. Offset cancellation technique and resistive averaging interpolation network improve the linearity. Cascading alleviates the wide-bandwidth requirement of the folding amplifier. In 0.18μm CMOS technology, the prototype A/D converter achieves 9.49 ENOB, 58.91 dB SNDR and 74.85 dB SFDR at Nyquist frequency input and 100MHz sample clock. The INL and DNL are within ±0.48 LSB and ±0.33 LSB, respectively. The chip occupies 2.29mm² active area and dissipates 95 mW at 1.8 V power supply.