13-bit 205 MS/s time-interleaved pipelined ADC with digital background calibration

This paper presents a 1.0-V 13-bit 205-MSample/s double-sampled pipelined analog-to-digital converter (ADC) with a 95-dB spurious free dynamic range (SFDR), a 75.5-dB signal-to-noise-plus-distortion ratio (SNDR) over the full Nyquist band and a total power consumption of 71 mW. This performance is enabled by digital background calibration of both capacitor mismatch in the multi-bit DAC and finite inter-stage gain errors. M-sequence characteristics was used for the generation of the multiple orthogonal codes needed in the calibration engine. Also, a simple design for the dithered re-quantizer which precedes calibration is adopted. Digital calibration achieves an improvement of better than 23-dB in SFDR and 13-dB in SNDR.