Title :
Synchronizers based on carrier phase lock Loop and on symbol phase lock loop
Author :
Reis, António D. ; Rocha, José F. ; Gameiro, Atilio S. ; Carvalho, José P.
Author_Institution :
Dep. de Electron. e Telecomun., Univ. de Aveiro, Aveiro
fDate :
Aug. 31 2008-Sept. 3 2008
Abstract :
The symbol synchronizer recoveries the clock and after, with it, samples and retimes the data. We present two synchronizer groups, the first based on filter with carrier phase lock loop (CPLL) and the second based on symbol phase lock loop (SPLL). Each group has four prototypes namely the analog, the hybrid, the combinational and the sequential. The objective is to study the various synchronizers output jitter UIRMS (unit interval root mean squared) as function of the input SNR (Signal to Noise Ratio).
Keywords :
analogue processing circuits; combinational circuits; filters; jitter; mean square error methods; phase locked loops; sequential circuits; synchronisation; CPLL; SPLL; UIRMS; analog circuit; carrier phase lock loop; clock recovery; combinational circuit; filter circuit; jitter; sequential circuit; symbol phase lock loop; symbol synchronizer; unit interval root mean square; Bit error rate; Clocks; Digital filters; Phase locked loops; Power harmonic filters; Signal to noise ratio; Switches; Synchronization; Telecommunications; Voltage-controlled oscillators; Synchronism in Digital Communications;
Conference_Titel :
Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on
Conference_Location :
St. Julien´s
Print_ISBN :
978-1-4244-2181-7
Electronic_ISBN :
978-1-4244-2182-4
DOI :
10.1109/ICECS.2008.4674845
