Title :
Comparative analysis of power yield improvement under process variation of sub-threshold flip-flops
Author :
Mostafa, Hassan ; Anis, Mohab ; Elmasry, Mohamed
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON, Canada
fDate :
May 30 2010-June 2 2010
Abstract :
In low power synchronous systems, sub-threshold flip-flops are used to reduce the total power dissipation. Moreover, process variations create a large variability in the flip-flop power in scaled technologies impacting the power yield, especially, for sub-threshold operation. This paper presents an analysis of power yield improvement of four commonly used flip-flops under process variations. These flip-flops are designed using STMicroelectronics 65-nm CMOS technology. The analyzed flip-flops are compared for delay, energy, and energy-delay product (EDP) overheads to achieve this power yield improvement. The analysis shows that the sense amplifier based flip flop (SA-FF) has the lowest overheads while the modified clocked CMOS master slave flip-flop (M-C2MOS-MSFF) exhibits the largest overheads, and correspondingly, it is not recommended for sub-threshold operation.
Keywords :
CMOS integrated circuits; flip-flops; logic design; low-power electronics; CMOS master slave flip-flop; energy-delay product; low power synchronous systems; power yield improvement; process variation; sense amplifier based flip flop; size 65 nm; sub-threshold flip-flops; CMOS technology; Circuit simulation; Clocks; Design methodology; Flip-flops; Latches; Master-slave; Power dissipation; Random processes; Threshold voltage;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537544
