Title :
High-speed and low-power programmable frequency divider
Author :
Chien, Ting-Hsu ; Lin, Chi-Sheng ; Wey, Chin-Long ; Juang, Ying-Zong ; Huang, Chun-Ming
Author_Institution :
Nat. Chip Implementation Center, Hsinchu, Taiwan
fDate :
May 30 2010-June 2 2010
Abstract :
This paper presents a novel 2/3 divider cell circuit design for a truly modular programmable frequency divider with high-speed, low-power, and high input-sensitivity features. In this paper, the proposed flip-flop based 2/3 divider cell adopts dynamic E-TSPC circuit that not only reduces power consumption, but also improves operation speed and input sensitivity. The whole design was implemented using the TSMC 0.18 μm 1P6M CMOS process. With an 8-stage 2/3 divider cell, the measurement results indicate that the proposed circuit operates up to 5.8 GHz with the power-consumption less than 3.24 mW.
Keywords :
CMOS logic circuits; flip-flops; frequency dividers; high-speed integrated circuits; integrated circuit design; logic design; low-power electronics; microwave integrated circuits; 2/3 divider cell circuit design; 8-stage 2/3 divider cell; CMOS; E-TSPC circuit; flip-flop based 2/3 divider cell; frequency 5.8 GHz; low-power programmable frequency divider; power consumption; size 0.18 mum; Circuit synthesis; Costs; Energy consumption; Flip-flops; Frequency conversion; Latches; Logic; Phase locked loops; Power dissipation; Voltage-controlled oscillators;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537546
