Neutron- and alpha-particle induced soft-error rates for flip flops at a 40 nm technology node

Author

Jagannathan, Srikanth ; Loveless, T.D. ; Diggins, Z. ; Bhuva, B.L. ; Wen, S.-J. ; Wong, R. ; Massengill, L.W.

Author_Institution

Dept. of EECS, Vanderbilt Univ., Nashville, TN, USA

fYear

2011

fDate

10-14 April 2011

Abstract

Flip-flop designs fabricated in a 40 nm bulk technology node with a wide range of soft-error hardness, area, power, and speed have been tested for neutron and alpha single event upsets. Neutron results show that the error rates of flip-flop designs that were considered hardened at older technologies are comparable to that of the conventional D-flip-flop. The soft-error rates (SER) of all the flip-flops consistently increase with reduction in supply voltage and increase in ambient temperature.

Keywords

flip-flops; logic design; alpha single event upsets; alpha-particle induced soft-error rate; bulk technology node; flip-flop design; neutron single event upsets; neutron-particle induced soft-error rate; size 40 nm; soft-error hardness; Alpha particles; CMOS integrated circuits; Flip-flops; Neutrons; Redundancy; Shift registers; Single event upset; D-FF; DICE; Radiation hardening; SER; SET; SEU; alpha; flip flop; neutron;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2011 IEEE International

Conference_Location

Monterey, CA

ISSN

1541-7026

Print_ISBN

978-1-4244-9113-1

Electronic_ISBN

1541-7026

Type

conf

DOI

10.1109/IRPS.2011.5784598

Filename

5784598