• DocumentCode
    3382188
  • Title

    Analysis of multiple cell upsets due to neutrons in SRAMs for a Deep-N-well process

  • Author

    Mahatme, Nihaar ; Bhuva, Bharat ; Fang, Y.-P. ; Oates, Anthony

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., Vanderbilt Univ., Nashville, TN, USA
  • fYear
    2011
  • fDate
    10-14 April 2011
  • Abstract
    This work accounts for the single-bit and multiple-cell upset phenomena due to neutron strikes in highly scaled SRAMs implemented in a Deep-N-well process. 3D TCAD simulations are used to explain test results, upset mechanisms and implications for ECC.
  • Keywords
    SRAM chips; error correction codes; neutrons; technology CAD (electronics); 3D TCAD simulations; SRAM; deep-N-well process; error correction code; multiple cell upsets; neutrons; Bipolar transistors; Error correction codes; Layout; MOSFETs; Neutrons; Random access memory; SRAMs; Soft-Error Rate; multiple-bit upset (MBU); multiple-cell upset (MCU); single-bit upset (SBU);
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Reliability Physics Symposium (IRPS), 2011 IEEE International
  • Conference_Location
    Monterey, CA
  • ISSN
    1541-7026
  • Print_ISBN
    978-1-4244-9113-1
  • Electronic_ISBN
    1541-7026
  • Type

    conf

  • DOI
    10.1109/IRPS.2011.5784599
  • Filename
    5784599
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3382188