Simultaneous bidirectional transceiver with impedance matching

This work presents a current-mode differential bidirectional transceiver with adaptive impedance matching architecture. The current signals are transmitted bidirectionally on a shared interconnection to double up the data rate. The voltage swing on the wire is reduced so that the proposed scheme consumes less power at higher data rate. The proposed adaptive impedance matching circuit has the ability to match wide range of resistance automatically and thus enhances the maximum data transfer rate by adding moderate power overhead which is suitable for both inter-chip and intra-chip transmission. Simulation using TSCM 0.18 mum CMOS process indicate that the proposed transceiver achieve a maximum data rate of 5 Gbps over on-chip wire of 1 mm dissipating power of 3.8 pJ.