Impact of ion-induced transients on high-speed dual-complementary Flip-Flop designs

This paper describes the single event performance of a dual-complementary D-type Flip-Flop (DC-DFF) implemented similarly to Dual Interlocked Cell (DICE-DFFs), but without pass-gates. Circuit-level modeling indicates that the DC-DFF is resistant to single event transient (SET) capture of errant signals on the data lines while increasing the operating speed, as compared to the DICE-DFF. However, the simulations also predict that the DC-DFF is susceptible to internal single events during data transitions. This susceptibility is not present in basic DICE designs, but is present in standard DFF designs. Heavy ion testing verified the simulations of the internal single-event clock-dependent mechanism in the DC-DFF design. This dynamic clock-dependent mechanism is described in detail.