A fast settling and low reference spur PLL with double sampling phase detector

This paper proposes a double sampling phase detector (DSPD) for the charge-pump phase-locked loop (PLL) design. The DSPD can double the PLL loop bandwidth to obtain the fast settling time and meanwhile shift the reference spur to higher frequency to suppress the reference spur. Verilog-AMS charge-pump PLL timing models with DSPD and conventional phase detector (PD) are developed to verify the fast settling time and low reference spur. By comparing the DSPD architecture to the conventional PD architecture, the settling time can be reduced 50% in the 30 ppm frequency accuracy and the reference spur can be suppressed 5.9 dB.