Stability improvement of a-ZIO TFT circuits using low temperature anneal

Author

Dey, Aritra ; Allee, David R.

Author_Institution

Flexible Display Center, Arizona State Univ., Tempe, AZ, USA

fYear

2011

fDate

10-14 April 2011

Abstract

Long duration of low temperature thermal anneals show performance and stability enhancement for low-temperature fabricated amorphous zinc-indium-oxide (a-ZIO) thin-film-transistors (TFTs). The turn-on voltage (V_on) of 50 hour annealed TFTs shifts by 1.5 V for a positive gate bias stress period of 10⁴ s when compared to a 2.2 V shift for the unannealed TFTs. The performance and stability improvements are attributed to a reduction of the interface trap density and removing of defects states in the band-gap of the a-ZIO.

Keywords

annealing; circuit stability; energy gap; interface states; thin film transistors; ZIO TFT circuit; ZIO thin-film-transistor; band-gap; interface trap density; low temperature thermal anneal; low-temperature fabricated amorphous zinc-indium-oxide; positive gate bias stress; stability improvement; turn-on voltage; voltage 1.5 V; voltage 2.2 V; Annealing; Degradation; Logic gates; Stress; Thermal stability; Thin film transistors; Zinc oxide; Dit; LCD; OLED; TFT; Von; Vth; ZIO; anneal; subthreshold swing;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2011 IEEE International

Conference_Location

Monterey, CA

ISSN

1541-7026

Print_ISBN

978-1-4244-9113-1

Electronic_ISBN

1541-7026

Type

conf

DOI

10.1109/IRPS.2011.5784601

Filename

5784601