Mapping of an N-Way Set Associative Cache to an N-Square Grid for the LRU Algorithm

The CPU memory delay gap is considered among the main issues in effecting the overall system performance. The cache system is introduce in the system to reduce the overall system delay time. The cache replacement policy is one of the most important factors that affect cache performance. With the trend of increasing associativity in second-level caches, implementing an effective replacement algorithm seems more challenging than just eliminating conflict misses. The contribution of this paper is in designing a practical circuit for the Least recently used (LRU) algorithm using a square grid that is easily mapped to an nxn grid of memory elements. The suggested method is seen to be mapped in a one to one basis to its corresponding hardware.