A new dynamic differential logic style as a countermeasure to power analysis attacks

Power analysis attacks exploit the existence of ldquoside channelsrdquo in implementations of cryptographic algorithms to extract secret data. The scientific literature reports consolidated methods - such as Differential Power Analysis (DPA) and Simple Power Analysis (SPA) - for extracting a secret cryptographic key through the sensing of the hardware power consumption. We propose a novel dynamic and differential CMOS logic style as a countermeasure against power attacks on cryptographic devices. The proposed logic family exploits the idea of using signals with 3 possible states and operates with power consumption ideally independent on both the logic values and the sequence of data. We have designed a set of logic gates, flip flops and a simple S-BOX, and compared the S-BOX against previously published secure logic styles in terms of transistor count, power consumption and correlation between data and power dissipation.