The AES in a systolic fashion: Implementation and results of Celator processor

A multi-algorithm Crypto-Co-Processor called Celator is presented. Celator architecture is based on a 4times4 Processing Elements systolic array, a Sequencer with a Finite State Machine (FSM) and a local memory, the Celator RAM (CRAM). Data are encrypted or decrypted by the PE array. The whole system architecture around Celator includes a Central Processing Unit (CPU) and an Interface unit between the CPU and Celator. The Sequencer controls the PE array and manages all the data transfers between the PE array and the CPU. Three multiplexers per PE allow the reconfigurability of the data path. The FSM instructions are stored in the CRAM and can be changed by the CPU: therefore the FSM is also reconfigurable. This paper focuses on the implementation of the Advanced Encryption Standard (AES) transformations on Celator. Celator can perform an AES encryption in 580 clock cycles in Electronic Codebook mode, which is less than with a general purpose processor. Finally we report performance comparisons among Celator, ARM 7 TDMI, ARM 9 and AVR microprocessors, as well as with some AES dedicated and dynamically reconfigurable circuits.