DocumentCode :
3382547
Title :
Improved lock-time in all-digital phase-locked loops due to binary search acquisition
Author :
Mendel, Stefan ; Vogel, Christian
Author_Institution :
Christian Doppler Lab. for Nonlinear Signal Process., Graz Univ. of Technol., Graz
fYear :
2008
fDate :
Aug. 31 2008-Sept. 3 2008
Firstpage :
384
Lastpage :
387
Abstract :
A binary search algorithm for an improved settling time in phase-domain all-digital phase-locked loops (ADPLLs) is proposed. Therefore, an ADPLL structure for high-speed fractional-N frequency synthesis is adapted to extract the ratio between the reference and the output frequency in each reference cycle. A frequency detector compares the obtained ratio to the ideal value. The proposed control algorithm uses the frequency detector output to iteratively search for the desired tuning word. The binary search acquisition speeds-up the acquisition process significantly and suits digitally controlled oscillators with multiple varactor banks well. Behavioral simulations illustrate the proposed technique.
Keywords :
digital control; digital phase locked loops; frequency synthesizers; phase locked oscillators; varactors; ADPLL structure; binary search acquisition process; digital control oscillator; frequency detector; high-speed fractional-N frequency synthesis; multiple varactor; phase-domain all-digital phase-locked loops; settling time; Bandwidth; Frequency conversion; Frequency synthesizers; Gears; Phase locked loops; Signal processing algorithms; Tuning; Varactors; Voltage-controlled oscillators; Wireless communication;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on
Conference_Location :
St. Julien´s
Print_ISBN :
978-1-4244-2181-7
Electronic_ISBN :
978-1-4244-2182-4
Type :
conf
DOI :
10.1109/ICECS.2008.4674871
Filename :
4674871
Link To Document :
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