MPSoC design of RT control applications based on FPGA SoftCore processors

Field programmable gate array (FPGA) based controller offer advantages such as high-speed complex functionality and low power consumption. According to the controller complexity, the FPGA design can be achieved by a multiprocessor system on chip (MPSoC) architectures with mixed software/hardware solutions. The aim of this paper is to design a full speed real time (RT) motor control drive algorithms for FPGA based MPSoC. To this purpose, a new approach is proposed to test controller design by implementing RT motor emulator linked to its controller drive in the same FPGA target. The gain with using this new approach is the ability to push past the operational limits of a specific environment and to test fault conditions that would otherwise be damaging or dangerous for a real motor. The developed MPSoC architectures consist of two and three SoftCore (MicroBlaze) processors that are linked by FIFO style communication. The implementation results, give an overview of MPSOC FPGA based controller benefits and illustrate the effect of interprocessor communication mode.