A CMOS 5.4/3.24Gbps dual-rate clock and data recovery design for DisplayPort v1.2

This paper presents a clock and data recovery (CDR) circuit that supports dual data rates of 5.4Gbps and 3.24Gbps for DisplayPort v1.2 sink device. The quarter-rate linear PD in the proposed CDR reduces jitter by enhancing the up and down pulse width. A charge pump (CP) is designed to compensate the different up and down pulse width of the PD and to reduce the current mismatch and power consumption. A voltage controlled oscillator (VCO) is designed with a “Mode” switching control for operating frequency selection. The measured RMS jitter of recovered clock signal is 3.0ps and the peak-to-peak jitter is 24.89ps under the simulation of a 2³¹-1 bit-long pseudo random bit sequence (PRBS) at the bit rate of 5.4Gbps. The chip area is 1.0mm × 1.3mm and the power consumption is 117mW from a 1.8V supply using 0.18μm CMOS process.