• DocumentCode
    3382699
  • Title

    PAMPR: Power-aware and minimum path routing algorithm for NoCs

  • Author

    Marvasti, Mohammadreza Binesh ; Daneshtalab, Masoud ; Afzali-Kusha, Ali ; Mohammadi, Siamak

  • Author_Institution
    Nanoelectron. Center of Excellence, Univ. of Tehran, Tehran
  • fYear
    2008
  • fDate
    Aug. 31 2008-Sept. 3 2008
  • Firstpage
    418
  • Lastpage
    421
  • Abstract
    In this paper, a novel adaptive routing model for avoiding congested areas through utilization of an adaptive routing table in two-dimensional mesh on-chip networks is proposed. The routing path is determined by minimizing a cost function which considers the path length and power consumption of the neighbor cores. The cells of routing table are updated dynamically by a coefficient which is a function of the minimum path and power consumption of the neighbors. The experimental results show that in comparison to other routing schemes, the power-delay product of our routing algorithm performs better under the transpose and hotspot traffic profiles with low hardware overhead.
  • Keywords
    network routing; network-on-chip; power aware computing; NoC; PAMPR; minimum path routing; network-on-chip; power-aware algorithm; two-dimensional mesh on-chip networks; Energy consumption; Network-on-a-chip; Routing; Switches; System recovery; System-on-a-chip; Telecommunication traffic; Tiles; Traffic control; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on
  • Conference_Location
    St. Julien´s
  • Print_ISBN
    978-1-4244-2181-7
  • Electronic_ISBN
    978-1-4244-2182-4
  • Type

    conf

  • DOI
    10.1109/ICECS.2008.4674879
  • Filename
    4674879