Low-power SOC implementation: What you need to know

Summary form only given. Power-gating and voltage scaling are two advanced power reduction methods in sub-65 nm production designs. The power-gating method reduces chip power in the sleep mode in which inactive blocks are shut down by turning off power supplies to the blocks through switch cells. The voltage scaling method lowers chip power by scaling down supply voltage to those parts of the design that operate at slow speed. Both methods are very effective and hence adopted in leading-edge low-power production designs. Implementations of such designs become very challenge due to design complexity introduced by the methods. This embedded tutorial address the challenges in advanced low-power SOC implementations and provides guidelines based on the years of experience in various advanced low-power production designs.