Title :
A 55nm 1GHz one-cycle-locking de-skewing circuit
Author :
Wang, Jinn-Shyan ; Cheng, Chun-Yuan ; Liu, Je-Ching ; Liu, Yu-Chia ; Wang, Yi-Ming
Author_Institution :
Dept. of EE, Nat. Chung-Cheng Univ., Chiayi, Taiwan
fDate :
May 30 2010-June 2 2010
Abstract :
This paper presents the design of a 55nm 1.0V 1GHz open-loop de-skewing circuit for clock synchronization in a SoC. All-digital architecture and circuit design techniques are adopted and developed to achieve small jitter, low power, super fast locking, and input duty-cycle independence. Even running at 1 GHz, the proposed circuit wakes up from sleep with only one-cycle locking time. Measurement results show a peak-to-peak jitter of 4 ps and a static phase error of 5.46 ps at 1 GHz. To the best of our knowledge, this is the first GHz open-loop de-skewing circuit achieving sub-μW/MHz active power. By power gating, 84% of leakage power is saved in the sleep mode.
Keywords :
clocks; integrated circuit design; synchronisation; system-on-chip; SoC; all-digital architecture; circuit design techniques; clock synchronization; frequency 1 GHz; one-cycle locking time; one-cycle-locking de-skewing circuit; open-loop de-skewing circuit; size 55 nm; system-on-chip; time 4 ps; time 5.46 ps; voltage 1.0 V; CMOS technology; Circuit synthesis; Clocks; Control systems; Delay; Energy consumption; Jitter; Open loop systems; Phase measurement; Synchronization;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537580
