DLX HOTOKADA: A design and implementation of a 32-bit dual core capable DLX microprocessor with single level cache

Author

Dioquino, Darryl Aldrin M ; Rosario, Katrina Joy S ; Supe, Homer F. ; Zarsuela, Jestoni V. ; Ballesil, Anastacia P. ; Reyes, Joy Alinda

Author_Institution

Dept. of Electr. & Electron. Eng., Univ. of the Philippines-Diliman, Diliman

fYear

2008

fDate

Aug. 31 2008-Sept. 3 2008

Firstpage

466

Lastpage

469

Abstract

Data access in main memory units can be sufficient for processors but due to demands for faster computers nowadays, implementation of multiple cores as well as the usage of a cache to increase performance, are necessary. These two solutions were implemented using a 32-bit pipelined DLX microprocessor, resulting to a dual core capable (DCC) DLX with single-level cache in a Uniform Memory Access Architecture type. This project made use of the Shared Cache System divided into an Instruction Cache and a Data Cache to solve processor structural hazards due to coincident instruction and data access.

Keywords

cache storage; microprocessor chips; 32-bit dual core pipelined DLX microprocessor; DLX HOTOKADA; shared cache system; single level cache; uniform memory access architecture type; Computer architecture; Ground penetrating radar; Hardware design languages; Laboratories; Memory architecture; Microprocessors; Multicore processing; Parallel processing; Registers; System performance;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on

Conference_Location

St. Julien´s

Print_ISBN

978-1-4244-2181-7

Electronic_ISBN

978-1-4244-2182-4

Type

conf

DOI

10.1109/ICECS.2008.4674891

Filename

4674891