Improving energy efficiency of functional units by exploiting their data-dependent latency

Conventional timing-optimized synchronous circuit is designed and constrained by the longest critical path delay, i.e. the worst-case design. However, the path delay of the circuit is absolutely data-dependent. In the example of an 8-bit multiplier simulation, for the 10,000 random input patterns, only about 1% of the input patterns exercise the critical path. This fact motivates us to exploit data-dependent latency of the functional unit to achieve significant energy reduction with negligible performance degradation. In this paper, we propose a design flow for the energy-efficient, variable-latency functional unit which exploits the data-dependent latency. In the 8-bit signed Booth-Wallace multiplier simulation (clock period: 1.2ns @UMC 90nm CMOS cell library), the proposed design can save energy by 21% with only 0.17% performance degradation. Besides, compared to other popular energy reduction technique, the pipelined architecture, for the classical 5-stage RISC processor, the proposed technique improves about 23-28% energy-delay metric performance efficiency.