Simultaneous co-design of distributed on-chip power supplies and decoupling capacitors

The effective design of power distribution networks has become highly challenging with each technology generation. The power delivery network is becoming large, making the system analysis process computationally complex. The large number of on-chip power supplies and intentional decoupling capacitors inserted throughout an integrated circuit further complicates the analysis of the power distribution network. To fully exploit the on-chip power supplies and decoupling capacitors, a new design methodology is required to simultaneously design the power distribution network that considers all of the power supplies and decoupling capacitors. Interactions among the power supplies, decoupling capacitors, and active circuitry are investigated in this paper utilizing a computationally efficient methodology. The effect of physical distance on the power supply noise is investigated. A design methodology for simultaneous placement of the on-chip voltage regulators and decoupling capacitors is also described in this paper. This methodology changes conventional practices where the power distribution network is designed first, followed by the placement of the decoupling capacitors.