Optimization and predication of leakage current characteristics in wide domino OR gates under PVT variation

Author

Gong, Na ; Sridhar, Ramalingam

Author_Institution

SUNY - Univ. at Buffalo, Buffalo, NY, USA

fYear

2010

fDate

27-29 Sept. 2010

Firstpage

19

Lastpage

24

Abstract

The leakage current characteristics of wide dual Vt domino OR gates is studied and gate-level models for estimating sub-threshold leakage and gate leakage current with two different sleep states are developed to determine the optimal sleep state. Results demonstrate that the developed models are robust and exhibit maximum error of 4% with respect to device-level BSIM4 models based HSPICE simulations. Furthermore, PVT variation aware leakage current characteristics of domino OR gates is analyzed and the optimal sleep state is obtained.

Keywords

SPICE; circuit simulation; leakage currents; logic circuits; logic gates; power supply circuits; temperature; HSPICE simulations; PVT variation aware leakage current characteristics; device-level BSIM4 models; gate leakage current; gate-level models; optimal sleep state; optimization; predication; sleep states; sub-threshold leakage; wide domino OR gates; wide dual Vt domino OR gates; Analytical models; Leakage current; Logic gates; MOSFETs; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference (SOCC), 2010 IEEE International

Conference_Location

Las Vegas, NV

ISSN

Pending

Print_ISBN

978-1-4244-6682-5

Type

conf

DOI

10.1109/SOCC.2010.5784663

Filename

5784663