Title :
Research on testing of 32-bit CPU based SiP
Author :
Xie, Chunlin ; Wu, Liji ; Zhang, Xiangmin
Author_Institution :
Tsinghua Nat. Lab. for Inf. Sci. & Technol., Tsinghua Univ., Beijing, China
Abstract :
With the increment of high density in integrated circuit, the usual one-single chip system has been replaced by SoC (System on Chip) and SiP (System in Package). In the SiP system, which is usually a multi-chips system, more than one chip are packaged together. A typical SiP includes a CPU and an erasable memory. The testing of SiP is one important aspect of SiP designing. This paper is mainly about the research and design of a testing system for SiP system, which includes Flash, EEPROM and a 32-bit CPU.
Keywords :
flash memories; integrated circuit testing; multiprocessing systems; system-in-package; system-on-chip; 32-bit CPU based SiP system; EEPROM; Flash; SiP system testing system; SoC; erasable memory; integrated circuit density; multichips system; one-single chip system; storage capacity 32 bit; system-in-package; system-on-chip; EPROM; Reliability; Software; EEPROM; Flash; SiP; Test;
Conference_Titel :
ASIC (ASICON), 2011 IEEE 9th International Conference on
Conference_Location :
Xiamen
Print_ISBN :
978-1-61284-192-2
Electronic_ISBN :
2162-7541
DOI :
10.1109/ASICON.2011.6157313
