Instruction level test for parallel multipliers

Multiplication operations are the normal operations in operating systems or scientific calculations. Multipliers embedded in processors, DSP or SoC are well optimized for best performance, and they are sensitive to test overhead. Instruction level test is a popular functional test approach for microprocessors test, and it can get satisfactory test results. But for the multipliers, one important part of microprocessors, there is no detail on how to testing them. This paper presents an instruction level test approach for the multiplier test. The proposed approach does not modify the multipliers and does not need any extra logic just using instructions of the processors to test processorspsila multipliers. Sequentially it does not have any test cost on area or timing. Moreover the instruction-level test is suited for at-speed test in nature. Experimental results on the real processorpsilas circuits show that the instruction level test approach has good effect on parallel multipliers.