A prediction-based, data Migration Algorithm for hybrid Architecture NoC systems

Multicore designs have been trending towards Network on Chip (NoC) Architectures since as early 2001. As these designs mature significant feature enhancement is still required. Cache latency for single accesses becomes a crippling design issue as the size of the chip expands. Even further, as usage patterns shift towards multiple accessors of a single datum, optimal placement becomes critical for fair cache latency among all users. Recent proposals have suggested reorganizing architecture in hybrid layouts with dense clusters of cores around cache banks to optimize data sharing. However even these NoCs will grow into large networks of multiple clusters as the core count rise into the hundreds. Therefore, additional cache policies must be implemented for optimal performance. In this paper we propose the Directional Migration Algorithm which is capable of small, rapid migrations between adjacent routers that will reduce cache latency in a hybrid NoC. We present the architecture in detail with simulations performed using the PARSEC benchmark suite against a theoretical Optimal Migration Algorithm. These experiments showed that while requiring a 87.1% smaller increase in cache space, the Directional Migration Algorithm could reduce cache latency to within 16% of that of a Optimal Migration Algorithm.