Title :
Parallel structure of GF (214) and GF (216) multipliers based on composite finite fields
Author :
Su, Jianing ; Lu, Zhenghao
Author_Institution :
Dept. of Electron. & Inf. Sci., Soochow Univ., Suzhou, China
Abstract :
In this paper, a parallel VLSI structure of multipliers in GF (214) and GF (216) is presented. The proposed parallel structure is based on de-composition of the original finite fields. The parallel structures can complete the finite field multiplication in a few clock cycles at the cost of endurable increase of logic area. The mapping matrices between binary and composite field representations of GF (214) and GF (216) are presented, as well as the heuristic search algorithm. Two BCH decoders that are based on GF (214) and GF (216) and using the proposed parallel Galois multiplier structures are implemented on FPGA. Complexity and data throughput analysis shows that it is suitable for cases which require finite field multiplications with high data throughput, such as BCH decoders in DVB broadcasting and nand-flash memories.
Keywords :
BCH codes; Galois fields; clocks; codecs; digital arithmetic; field programmable gate arrays; multiplying circuits; BCH decoder; DVB broadcasting; FPGA; GF (214) multiplier; GF (216) multiplier; VLSI structure; clock cycles; composite finite field; heuristic search algorithm; logic area; nand-flash memory; parallel Galois multiplier structure; parallel structure; Logic gates; Finite fields; bit-parallel Galois multiplier; composite fields; heuristic search; mapping matrix;
Conference_Titel :
ASIC (ASICON), 2011 IEEE 9th International Conference on
Conference_Location :
Xiamen
Print_ISBN :
978-1-61284-192-2
Electronic_ISBN :
2162-7541
DOI :
10.1109/ASICON.2011.6157318
