GALEOR: Leakage reduction for CMOS circuits

High performance and computational capability in the current generation processors are made possible by small feature sizes and high device density. To maintain the current drive strength and control the power dissipation in these processors, simultaneous scaling down of supply and threshold voltages is performed. High device density and low threshold voltages result in an increase in the leakage current dissipation. Large on chip caches are integrated onto the current generation processors which are becoming a major contributor to total leakage power. The proposed static power reduction technique, GALEOR (GAted LEakage TransistOR), reduces the leakage current flowing through the circuits. In the proposed leakage power technique, two gated leakage transistors are inserted between NMOS and PMOS circuitry of the existing circuit such that gates of the extra inserted transistors are connected to their respective drain regions. GALEOR technique was tested on standard cell gates and memory elements. Area overhead is minimized by eliminating the use of control logic to switch between the active and standby states. Performance overhead is increased due to the reduced output voltage swing.