A reconfigurable linear array processor architecture for data parallel and computation intensive applications

Recent embedded systems have switched to parallel microprocessors. Linear array processors and 2-D array processors are two classifications for the processing element (PE) interconnection. The former have better expansibility and greater throughput while the later have better communication efficiency. In order to improve the communicat ion efficiency without losing expansibility, this paper introduces RLAP, a reconfigurable linear array processor architecture, targeted at data parallel and computation intensive applications in the video domain. Compared with the conventional linear array processors, the performance of RLAP improves by 8.7 times, 104% and 10.8% for the applications of 8×8 matrix transpose, 8×8 DCT and 16×16 SAD.