Title :
Low power VLSI architectures for variable-length encoding and decoding
Author :
Molloy, Stephen ; Jain, Rajeev
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Abstract :
New low power VLSI architectures are presented for variable-length encoding and decoding. Look-up table partitioning by symbol probability is shown to reduce the total power consumption; the variable-length decoder and encoder are reduced by as much as 66% and 75%, respectively. Design examples for a subband image CODEC are presented with measurements from extracted VLSI layouts.
Keywords :
VLSI; codecs; data compression; image coding; probability; table lookup; VLSI layouts; look-up table partitioning; low power VLSI architectures; subband image CODEC; symbol probability; total power consumption; variable-length decoding; variable-length encoding; Decoding; Encoding; Energy consumption; Equations; HDTV; Image coding; Table lookup; Throughput; Very large scale integration; Video compression;
Conference_Titel :
Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on
Print_ISBN :
0-7803-3694-1
DOI :
10.1109/MWSCAS.1997.662244
