• DocumentCode
    3383475
  • Title

    An architectural survey and modeling of data cache memories in Verilog HDL

  • Author

    Crisu, Dan

  • Author_Institution
    Fac. of Electron. & Telecommun., Politehnica Univ. of Bucharest, Romania
  • Volume
    1
  • fYear
    1999
  • fDate
    1999
  • Firstpage
    139
  • Abstract
    In this paper two data cache architectures-a direct-mapped write-through data cache and a direct-mapped, write-through, write buffering data cache-are presented followed by a synthesized implementation of these data cache models. Strategies for testing, results of simulations with Verilog-XLTM and methods of architectural improvement are also given
  • Keywords
    cache storage; hardware description languages; memory architecture; Verilog HDL; data cache memory architecture; direct-mapped write-through data cache; direct-mapped write-through write buffering data cache; simulation model; Hardware design languages; Hazards; Laboratories; Pipelines; Random access memory; Read-write memory; Reduced instruction set computing; Signal processing; System buses; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Semiconductor Conference, 1999. CAS '99 Proceedings. 1999 International
  • Conference_Location
    Sinaia
  • Print_ISBN
    0-7803-5139-8
  • Type

    conf

  • DOI
    10.1109/SMICND.1999.810448
  • Filename
    810448
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3383475