Hierarchical data structure-based timing controller design for plasma display panels

In this paper, we propose a timing controller design to use a hierarchical structure of control signals for plasma display panels (PDPs). Also, we used a double buffering and a repeatable FIFO in order to reduce the workload of memory accesses for control data, and provided a graphical user interface program for easy control data management. Our prototype system runs at 83 MHz on Spartan-3A DSP FPGA, and the new design achieves the reduction of 73 % in resource usage from the previous implementation.