Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation

We present a fine-grained assist bias control technique for enhancing read-/write-margins of embedded SRAM in deep-submicron SoC. This technique controls the individual assist bias for finely segmented rows and columns of a cell array with small area overheads. We design and fabricate prototype micro-controller test chips with 1 Mb SRAM using 90-nm low-standby-power CMOS technology. The evaluation results demonstrate that V_min achieves 0.64 V, which is a 21% improvement compared to the conventionally used technique.