Energy efficient computation with self-adaptive single-ended body bias

Energy efficient computation becomes increasingly important for battery driven ubiquitous computing applications. To extend the battery life time while still meeting the performance demands, the designers face critical challenges in choosing the appropriate circuit topologies and low-power design techniques in order to optimally balance the power and performance trade-offs. In this paper, we evaluate various form of single-ended body bias configuration and experimented the fine-grained self-adaptive circuit optimization technique such as pull-up body bias and pull-down body bias to combine the monotonic precharge-evaluate logic circuits and application of body bias based on the evaluation and idle modes within logic stages. This technique improves the evaluation delay by 19% and 16% with 15% and 10% lower energy consumption for the non-clocked and clocked 16-bit CLA adder respectively.