DocumentCode
3383591
Title
TSV based 3D IC wire length calculation algorithm
Author
Hou, Ligang ; Bai, Shu ; Wang, Jinhui
Author_Institution
VLSI & Syst. Lab., Beijing Univ. of Technol., Beijing, China
fYear
2011
fDate
25-28 Oct. 2011
Firstpage
816
Lastpage
819
Abstract
This paper forwards a novel wire length calculation algorithm based on TSV position. Typical 2D wire length calculation method such as half-perimeter model does not take via position into account. But in 3D IC placement, TSV position does affect the real wire length which is ignored in previous works. To get accurate wire length data and help 3D placement researches, this paper forwards the TSV based 3D IC wire length algorithm. Experiments are done on folded placement results of IBM placement benchmark circuits. Results shows that this algorithm can effectively identify the difference wire length of the cross wafer net according to the traditional method and calculate it accurately.
Keywords
integrated circuit layout; integrated circuit modelling; three-dimensional integrated circuits; 2D wire length calculation method; 3D IC placement; IBM placement benchmark circuits; TSV based 3D IC wire length calculation algorithm; TSV position; cross wafer; half-perimeter model; via position; Three dimensional displays; Through-silicon vias; Transforms; Yttrium;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC (ASICON), 2011 IEEE 9th International Conference on
Conference_Location
Xiamen
ISSN
2162-7541
Print_ISBN
978-1-61284-192-2
Electronic_ISBN
2162-7541
Type
conf
DOI
10.1109/ASICON.2011.6157330
Filename
6157330
Link To Document