An ultra-low power consumption 1-V, 10-bit succesive approximation ADC

An ultra-low power consumption 10-bit rail-to-rail input range successive-approximation Analog-to-Digital Converter (ADC) for sensor network applications is presented. It is designed in a standard 0.13 mum CMOS process technology. The converter consists of a capacitor-based digital-to-analog converter, a two-stage voltage comparator, formed by a pre-amplifier and a dynamic-latch, a passive sample-and-hold circuit, a current reference generator and digital circuitry for switching and control. Post-layout simulations show that the ADC consumes less than 2 muW at a conversion rate of 100 kS/s from a 1 V voltage supply. Proper operation is achieved down to a supply voltage of 0.8 V.