A power-efficient capacitor structure for high-speed charge recycling SAR ADCs

A novel capacitor array structure for successive approximation register (SAR) ADC is proposed. This circuit efficiently utilizes charge recycling to achieve high-speed of operation and it can be applied to low-to-medium-resolution, high-speed SAR ADC´s. The parasitic effects of the proposed structure are analyzed theoretically and behavioral simulations are presented to verify the circuit´s performance under those non-idealities. The simulation results show that the proposed capacitor array structure can reduce the average power consumed in the capacitor array by 90% when compared to the binary-weighted splitting capacitor method.