A design methodology for protocol processors

New communication protocols such as FCS (Fibre Channel Standard), and ATM (Asynchronous Transfer Mode), are the emerging gigabit network standards. The emergence of these gigabit speed networks has resulted in increased communication processing requirements. Numerous architectures have been developed (using transputers, multiple microprocessors, VLSI, or high performance host machine) to meet such processing requirements. In this paper, we classify those architectures and discuss their pros and cons. We also propose an architecture using homogeneous multi-processors in a single VLSI chip. Given the state-of-the-art in CAD (Computer Aided Design) systems and the wide acceptance of IEEE VHDL (VHSIC Hardware Description Language) as the industry standard, it is now possible to build VHDL macro libraries and use them in designing environment-specific VLSI protocol processors. Libraries of behavioral models, typically used in simulating modules and adapter cards, can also be re-utilized in order to make the design process shorter, simpler and more cost-effective. We call this approach CVDS (Communication VLSI Design System)