A reconfigurable successive approximation ADC in 0.18μm CMOS technology

This paper presents the design of a reconfigurable successive approximation analog to digital converter (ADC) for both ultra wideband and Bluetooth applications. The behavioral level design is presented along with the circuit implementation. The ADC architecture employs a split capacitor array DAC which reduces the power consumption. The ADC is implemented in a 0.18mum CMOS process and circuit level simulation results show that the ADC can achieve 28.9 dB SINAD at 66 MSPS in the UWB mode, and 53.9 dB SINAD at 1 MSPS in the Bluetooth mode.