Design of cost-efficient multipliers modulo 2a−1

In this paper, we propose a new design method for modulo 2^a-1 multipliers which accept double representation of 0 of input operands. The new multiplier takes advantage of the symmetric properties of integers written in l´s complement representation which allows to reduce the size of carry-save adders (CSAs) used. Currently, for small a they are the least complex (in terms of the number of logic gates) multipliers modulo 2^a-1 available in the open literature.