Title :
Single event upset mitigation for FDP2008
Author :
Yang, Meng ; Chen, Gengsheng
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
Abstract :
Highly integrated contemporary SRAM-based Field Programmable Gate Arrays (FPGAs) lead to high occurrence-rate of transient faults induced by Single Event Upsets (SEUs) in FPGAs´ configuration memory. In this paper, Fudan Design Environment (FDE) Triple Module Redundancy (TMR) approach for design triplication has been devised to meet high-reliability design on FDP2008. Throughput Logic, feedback logic, I/O logic and special feature such as Shift Register LUTs (SRLs) and constant logic are treated differently to effectively mitigate the effects of the SEU faults.
Keywords :
SRAM chips; field programmable gate arrays; radiation effects; FDP2008; Fudan design environment; configuration memory; constant logic; field programmable gate arrays; highly integrated contemporary SRAM; shift register LUT; single event upset mitigation; single event upsets; transient faults; triple module redundancy approach; Europe; Radiation hardening; Tunneling magnetoresistance;
Conference_Titel :
ASIC (ASICON), 2011 IEEE 9th International Conference on
Conference_Location :
Xiamen
Print_ISBN :
978-1-61284-192-2
Electronic_ISBN :
2162-7541
DOI :
10.1109/ASICON.2011.6157337
