Design error diagnosis and correction in VLSI digital circuits

With the increase in the complexity of VLSI circuit design and the corresponding increase in the number of logic gates on a chip, logic design errors can frequently occur. In this paper we present an efficient test-vector simulation approach for design error diagnosis when a small number of modifications can rectify the erroneous design. We also compare the quality of verification and diagnosis that test vector simulation offers for design errors with the one offered by BDDs and show the competitive performance of the former. Experimental results exhibit the robustness of our approach.