• DocumentCode
    3383888
  • Title

    Design and implementation of pipelined TMVP multiplier using block recombination

  • Author

    Ma, Xiao ; Bai, Guoqiang

  • Author_Institution
    Tsinghua Nat. Lab. for Inf. Sci. & Technol., Tsinghua Univ., Beijing, China
  • fYear
    2011
  • fDate
    25-28 Oct. 2011
  • Firstpage
    874
  • Lastpage
    877
  • Abstract
    Fan and Hasan proposed a new scheme for subquadratic space complexity parallel multiplication in GF(2n) using Toeplitz matrix-vector products (TMVP). Recently, a recombined version of Fan-Hasan TMVP multiplier is also proposed to achieve lower space complexity. In this paper, optimal ending condition during recursion for the recombined multiplier is discussed. Based on the idea of decomposing building blocks, we present a new method to design pipelined parallel binary field multiplier which has subquadratic space complexity in combinational part and high throughput. ASIC results of this proposed multiplier are shown to have total area saving of 28.8% with even better throughput against designs using brute force algorithm when optimized for speed.
  • Keywords
    application specific integrated circuits; logic design; multiplying circuits; ASIC; Fan-Hasan TMVP multiplier; Toeplitz matrix-vector products; block recombination; pipelined TMVP multiplier; pipelined parallel binary field multiplier; subquadratic space complexity parallel multiplication; Delay; Logic gates; Matrix decomposition;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC (ASICON), 2011 IEEE 9th International Conference on
  • Conference_Location
    Xiamen
  • ISSN
    2162-7541
  • Print_ISBN
    978-1-61284-192-2
  • Electronic_ISBN
    2162-7541
  • Type

    conf

  • DOI
    10.1109/ASICON.2011.6157344
  • Filename
    6157344