Memory-reduced MAP decoding for double-binary convolutional Turbo code

This paper presents a memory-reduced VLSI architecture for the decoding of double-binary convolutional Turbo code (DB CTC) using maximum a posteriori probability (MAP) algorithm. For such kind of soft-in soft-out (SISO) decoding, the branch metrics (BMs) γ become the dominant factor in determining the overall required memory size inside the SISO decoder. We propose to decompose each BM into a information metric and a parity metric, which leads to 50% reduction of the memory size for BMs. We further modify the MAP algorithm based on the new formulation of BMs. The new MAP algorithm reveals that: 1) the partitioning of BMs does not introduce any computational overhead when the MAP algorithm is modified; 2) the extrinsic metrics are independent from a posteriori log-likelihood ration, which is attractive for low-power SISO decoder design.