Design of current reuse CMOS LC-VCO

This paper describes the design of voltage controlled oscillator (VCO) with a low-power static frequency divider. The new LC-VCO replaces one of the NMOS of a conventional differential LC-VCO with a PMOS, which reduces power dissipation to the half and allows operation at reduced supply voltages. Based on a 0.13um UMC CMOS process, the VCO is simulated using 0.8V supply voltage. It is demonstrated that the proposed N-&P-MOS cross-coupled pair VCO operating at 806MHz can work with a power consumption of 0.24mW with as low as - 133dBc/Hz of phase noise at 1-MHz offset. Finally, in order to generate the quadrature signals at 403MHz, a low-power static frequency divider is designed, which utilizes a parallel switching current topology.