A 10-b 100-MS/s pipelined ADC with an optimized bit-stage resolution in 65nm CMOS technology

In this paper the design of a 10b 100-MS/s pipeline analog-to-digital converter (ADC) with an optimized bit-stage resolution is presented. A careful analysis of the ADC architecture is presented. The proposed architecture is made by two main stages with opamp-sharing technique and a 3b full-flash ADC. The 1^st stage has a 1.5b resolution architecture, the remaining stages have 2.5 b resolution architecture. Furthermore, the input sampling is directly performed on the 1^st stage. The ADC is implemented in 65 nm digital CMOS process technology. It achieves 69.3 dB spurious-free-dynamic-range (SFDR), 59.3 dB signal-to-noise ratio (SNR), 9.6 effective number of bits (ENOB) for a 49 MHz input at full sampling rate. The ADC power consumption is about 12.7 mW from a 1.2 V supply. The FOM value is about 165 fJ/conv. It occupies 0.8mm².