A novel soft error sensitivity characterization technique based on simulated fault injection and constrained association analysis

Soft error, a concern for space applications in the past, became a critical issue in deep sub-micron VLSI design for the continuous technology scaling. Automated fault injection technique is employed to characterize the soft error sensitivity of VHDL based design and association analysis algorithm is firstly introduced into this realm to explore the fault dependency of the components in the design. The association analysis technique makes the soft error characterization more systematic and methodic. An automated simulation based fault injector HSECT (HIT Soft Error Characterization Toolkit) is designed and a simple RISC processor, DP32-processor is selected as the research prototype. By using HSECT, 30,000 soft errors are injected to the DP32-processor with good statistical significance. The soft error sensitivity of the processor and the fault dependency of its components are also further investigated to direct the future design of the fault-tolerant and dependable circuits.