Improved algorithm for Pareto front computation for CMOS OpAmp based on multi-objective genetic optimization

The Pareto front permits the circuit designer to select optimal tradeoff from multiple performance objectives and received much attention in the analog design automation community recently. Now the dominant approach to find the Pareto front is through multi-objective genetic optimization, which requires large amount of computations since the embedding of a circuit simulator in the optimizing loop. We propose in this paper an improved algorithm for the Pareto front computation. By combing the analytical equation based optimization with the simulation based approach, the resulted two-stage algorithm accelerates the Pareto front seeking process significantly. The method is illustrated with the example of a Miller-compensated operational transconductance amplifier.